An Interview with Computer Science Department Chair

Constructing highly detailed 3-D models of large complex sites using range scanners can be a time consuming manual process. One of the main drawbacks is determining where to place the scanner to obtain complete coverage of a site. We have developed a system for automatic view planning called VuePlan. The system proceeds in two distinct stages. In the initial phase, the system is given a 2-D site footprint with which it plans a minimal set of sufficient and properly constrained covering views. We then use a 3-D laser scanner to take scans at each of these views. When this planning system is combined with our mobile robot, it automatically computes and executes a tour of these viewing locations and acquires them with the robot’s onboard laser scanner. These initial scans serve as an approximate 3-D model of the site. The planning software then enters a second phase in which it updates this model by using a voxelbased occupancy procedure to plan the next best view (NBV). This next best view is acquired, and further NBVs are sequentially computed and acquired until an accurate and complete 3-D model is obtained. A simulator tool which we developed has allowed us to test our entire view planning algorithm on simulated sites. We have also successfully used our two-phase system to construct precise 3-D models of real world sites located in New York City: Uris Hall on the campus of Columbia University and Fort Jay on Governors Island. John Cieslewicz Advisor: Professor Kenneth Ross ArchitectureSensitive Database Query Processing on Chip Multiprocessors Abstract: Microprocessor design is currently in the midst of a sea change, which will have a significant impact on all computer applications including database management systems, the focus of this thesis. For the past several decades, microprocessor performance has been driven primarily by higher clock rates and the subsequent faster execution of a single stream of instructions (a single thread). Faster chip speeds require more power and produce more heat. A single thread also has difficulty providing enough work to keep a chip busy because applications often have to wait for high latency operations such as loading data from memory, an operation that becomes more expensive in terms of processor cycles the faster a chip is. For these reasons, processor architects have recently begun to improve processor performance by increasing the degree of onchip thread-level parallelism rather than the chip speed. The processor designs featuring on-chip parallelism are termed chip multiprocessors and include multi-core and simultaneous multithreading processors, both of which are examined in this thesis. Microprocessor design is currently in the midst of a sea change, which will have a significant impact on all computer applications including database management systems, the focus of this thesis. For the past several decades, microprocessor performance has been driven primarily by higher clock rates and the subsequent faster execution of a single stream of instructions (a single thread). Faster chip speeds require more power and produce more heat. A single thread also has difficulty providing enough work to keep a chip busy because applications often have to wait for high latency operations such as loading data from memory, an operation that becomes more expensive in terms of processor cycles the faster a chip is. For these reasons, processor architects have recently begun to improve processor performance by increasing the degree of onchip thread-level parallelism rather than the chip speed. The processor designs featuring on-chip parallelism are termed chip multiprocessors and include multi-core and simultaneous multithreading processors, both of which are examined in this thesis. The move toward on-chip parallelism has important implications for computer applications. Database management systems are a core computer application used across disciplines within computer science and in almost every sector of the economy. This means that database performance has a big impact on most data related activities. This thesis examines the performance of several core database operations on different chip multiprocessor architectures. Performance challenges are identified and architecturesensitive algorithms designed specifically for chip multiprocessors are proposed and verified. Three core challenges impact database performance on chip multiprocessors: (1) identifying sufficient parallelism with database operations to take advantage of on-chip parallelism, (2) managing shared on-chip resources including memory cache, memory bandwidth, and execution units, and (3) balancing the aforementioned resource sharing with inter-thread communication overhead. The first part of this thesis examines the use of simultaneous multithreading technology to help overcome performance bottlenecks due to high memory latency in common database join algorithms. Then a highly parallel supercomputer is used to demonstrate the benefits of massively parallel architectures for data processing tasks. Finally, the last sections examine core database operations on a commodity chip multiprocessor with the highest currently available degree of on-chip parallelism. Chip multiprocessors are shown to have significant benefits for database performance, but achieving optimal performance requires database algorithms to be crafted with on-chip parallelism as a design parameter from the start. Frank Enos Advisor: Professor Julia Hirschberg Detecting Deception in Speech This dissertation describes work on the detection of deception in speech using the techniques of spoken language processing. The accurate detection of deception in human interactions has long been of interest across a broad array of contexts and has been studied in a number of fields, including psychology, communication, and law enforcement. The detection of deception is well-known to be a challenging problem: people are notoriously bad lie detectors, and no verified approach yet exists that can reliably and consistently catch liars. To date, the speech signal itself has been largely neglected by researchers as a source of cues to deception. Prior to the work presented here, no comprehensive attempt has been made by speech scientists to apply state-of-the-art speech processing techniques to the study of deception. This work uses a set of features new to the deception domain in classification experiments, statistical analyses, and speakerand group-dependent modeling approaches, all designed to identify and employ potential cues to deception in speech. This dissertation shows that speech processing techniques are relevant to the deception domain by demonstrating significant statistical effects for deception on a number of features, both in corpus-wide and subjectdependent analyses. Results also show that deceptive speech can be automatically classified with some success: accuracy is better than chance and considerably better than human hearers performing an analogous task.